1. Field of the Invention
The present invention relates to an ESD protection circuit and particularly to an ESD protection circuit with tunable gate-bias.
2. Description of the Prior Art
Traditional gate-driven or gate-coupled techniques are widely used in ESD protection circuit design. These two techniques can provide a gate-bias voltage of the ESD protection device under ESD-stress conditions. With the gate-bias voltage, the trigger voltage of the ESD protection device can be reduced, and the turn-on uniformity and turn-on efficiency can be enhanced.
FIG. 1 is a diagram showing a conventional gate-coupled input ESD protection circuit. The input ESD protection circuit includes an NMOS transistor MNESD providing the source and drain respectively coupled to a VSS and input pad, a PMOS transistor MPESD with the source and drain coupled to a VDD pad and the input pad, resistors R1 and R2 respectively coupled between the gate of the transistor MNESD and VSS pad, and the gate of the transistor MPESD and VDD pad, and capacitors C1 and C2 respectively coupled between the gate of the transistor MNESD and input pad, and the gate of the transistor MPESD and input pad.
The capacitors C1 and C2 are used to couple the ESD transient voltage from the input pad to the gate of the ESD protection transistors MNESD and MPESD. With a coupled voltage on the gate of the ESD protection transistors MNESD and MPESD, all the fingers of the ESD protection transistors MNESD and MPESD can be uniformly turned on to bypass the ESD current and dissipate the charge from the input pad.
FIG. 2 is a diagram showing a conventional gate-driven ESD protection circuit between the power supply voltage source VDD and the substrate biasing voltage source VSS pad. The circuit includes a PMOS transistor MP1 with the bulk and source commonly coupled to a VDD pad, an NMOS transistor MN1 with the bulk and source commonly coupled to a VSS pad, and the gate and drain respectively coupled to the gate and drain of the transistor MP1, a resistor R coupled between the VDD pad and the gates of transistors MP1 and MN1, a capacitor C coupled between the VSS pad and the gates of the transistors MP1 and MN1, and an NMOS transistor MNESD with the gate coupled to the drains of the transistor MP1 and MN1, and the source and drain respectively coupled to the VSS and VDD pad. When a positive ESD pulse is applied to the VDD pad, a transient voltage difference is generated across the resistor R and turns on the transistor MP1, which increases the gate voltage of the transistor MNESD and turns on the transistor MNESD so that an ESD current path from the VDD to the VSS pad is formed through the turned-on MNESD.
FIG. 3 is a diagram showing another conventional gate-driven ESD protection circuit. It is noted that there are two transistors MP2 and MN2 additional to the circuit shown in FIG. 2. The operation of the circuit is similar to that of the circuit in FIG. 2. When a positive ESD pulse is applied to the VDD pad, a transient voltage difference is generated across the resistor R and turns on the transistor MP1, which increases the gate voltage of the transistor MN2 and turns on the transistor MN2. Thus, the gate voltage of the transistor MPESD is pulled down to the VSS and turns on the transistor MPESD so that an ESD current path from the VDD to the VSS pad is formed through the turned-on MPESD.
However, in the deep-submicron CMOS process, if the voltage level at the gate of the ESD protection NMOS transistor MNESD is at a high voltage level during the extreme voltage level from contact with an ESD source, a surface channel of the ESD protection NMOS transistor MNESD is formed, and the ESD current is discharged through the much shallower surface channel of the ESD protection NMOS transistor MNESD. The ESD current is often on the order of several amperes (A). For example, a 2-KV human-body-model (HBM) ESD event can generate an ESD current of about 1.33 A. Such a large ESD current flowing through the shallower surface channel forces a very high current density and can easily destroy the ESD protection NMOS transistor MNESD even if the ESD protection NMOS transistor MNESD has a relatively huge device dimension. This phenomenon generally causes a much lower ESD voltage level to be sustained by the ESD protection NMOS transistor MNESD. This phenomenon has been referred to as the “overstress gate-driven effect”. Thus, there exists a design window for the gate-bias voltage, which is explained in J. Chen et al, “Design Methodology and Optimization of Gate-Driven NMOS ESD Protection Circuits in Submicron CMOS Processes”, IEEE Trans. on Electron Devices, vol. 45, No. 12, pp. 2448–2456, December 1998. If too high the gate-bias voltage is applied, the ESD immunity of the ESD protection device will degrade. The suitable range of the gate-biased voltage of the ESD protection device mainly depends on technology and the process itself.
To solve the problem, U.S. Pat. No. 6,249,410 provides ESD protection circuits without overstress gate-driven effect, as shown in FIG. 4˜6. It is noted that the circuits in FIG. 4˜6 are derived by adding a diode between the gate and the source of each ESD protection transistor in FIG. 1˜3. To prevent excess voltage from forming, when the ESD pulse is applied to the pad, the diode is turned on to clamp the voltage level on the gate of the ESD protection transistor at a level sufficient to turn on the ESD protection transistor but not cause damage.
The present invention provides other novel gate-driven and gate-coupled ESD protection circuits with tunable gate-bias to prevent the ESD immunity degradation due to the overstress gate-driven effect.